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eeDesign is the comprehensive source of information for electronics design tools and methodologies. Its scope includes EDA tools, silicon intellectual property (IP), chip design methodologies, and chip and system architectures. Your feedback is welcome.


  eeDesign Exclusives
Practical Power Network Synthesis For Power-Gating Designs
The article describes a method for properly sizing sleep transistors in power network synthesis. It introduces the concept of a "fake via" to enable power network synthesis using existing EDA tools.More »

  Headlines for Monday Dec 1, 2008
Business
  • Americas actual chip sales fell 22% in October, says WSTS
  • October chip sales down 10.4% year-on-year, says WSTS
  • Global chip sales fell 2.4% in October, says SIA
  • Comment: Reading Cadence's tea leaves
    Technology
  • SoCs to bring femtocell costs down
    Products
  • LTE chips get ready to roll
  • Retro wireless: Hoffman RT-159A/URC-4 survival radio


      Headlines for Sunday Nov 30, 2008


      Headlines for Friday Nov 28, 2008
    Business
  • TSMC, UMC looking to cut costs by 20%, says report
    Products
  • Nujira touts PA efficiency advance in handsets


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      Design Resources
    Designing for a dual Galileo-based GPS system
    Malcolm Lomer of SiGe Semiconductor discusses GPS design challenges with the Galileo satellite system.
    More »
     

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